The present invention relates to semiconductor integrated circuits and their manufacture. The invention is illustrated in an example with regard to the manufacture of a storage cell capacitor for a dynamic random access memory (DRAM) integrated circuit, but it will be recognized that the invention has a wider range of applicability. Merely by way of example, the invention may be applied in the manufacture of other semiconductor devices such as local interconnection for SRAM, among others.
Capacitors and metal oxide field effect (MOS) transistors and their manufacture are generally known in the art. In the fabrication of a DRAM integrated circuit, it is necessary to fabricate a DRAM cell which includes the MOS transistor and a storage cell capacitor. Examples of DRAM cells include the single poly/diffused bit line cell and double poly diffused bit line cell structures. These cell structures are often not compatible in the manufacture of present DRAM integrated circuits having smaller line widths and greater memory capacity.
In the single poly/diffused bit line DRAM cell structure, each cell includes a field effect transistor (FET) that is adjacent to a storage cell capacitor, thereby providing a substantially linear configuration on the semiconductor substrate. This cell structure typically occupies a larger region which often limits the amount of cells that can be fabricated onto the substrate. Accordingly, the single poly/diffused bit line cells are often not desirable when forming a densely packed structure typically needed for the higher memory DRAM integrated circuits.
Other cell structures such as the double poly/diffused bit line cell are also limiting for the higher memory DRAM integrated circuits. Though such cell may form a densely packed unit for each DRAM device, other limitations often exist, typically lower capacitance of the storage cell capacitor and undesirable capacitance variations among different lines of the DRAM cells.
Further problems may occur during the manufacture of higher memory DRAM integrated circuits by use of the above-mentioned cell structures. For example, as line widths become smaller in the DRAM integrated circuit, mask alignment often becomes more difficult to perform accurately, especially at a critical masking step. This is likely to cause misalignment which often decreases the yield of the integrated circuit devices on a typical semiconductor wafer. Accordingly, it is often desirable to reduce the number of critical masking steps or provide a process that has self-aligning steps.
In addition, multiple implanting steps, especially for high-dose arsenic implants, of the source/drain regions of the field effect devices in both the core region and peripheral region are likely to create more damage to shallower diffusions of semiconductor in the denser DRAM cells. Such damage to the semiconductor often creates current leakage of the core memory area, among other related problems, thereby decreasing the reliability and performance of the particular semiconductor integrated circuit. In a conventional DRAM integrated circuit, at least three separate implanting steps of separate source/drain regions are performed, typically increasing the damage to the semiconductor in the core memory region.
Further, the increased device complexity of the higher memory DRAM integrated circuits often creates more process steps. More process steps are likely to increase the possibility of introducing defects into the device, typically caused by particles, operator handling, and the like. More process steps also tend to promote a longer product turn-around-time (TAT), typically defined as the time from wafer start to final test for the manufacture of the DRAM integrated circuit. The longer TAT is also likely to create higher costs in the manufacture of the integrated circuit.
Still further, it is often desirable to manufacture devices with features therein for easy identification. Competition in the semiconductor industry creates a need for identifying products for the purpose of infringement. Piracy of semiconductor designs also continues to increase as world-wide demand for semiconductor chips grows. However, it is often difficult to determine whether a competitor's chip actually infringes a patented process or has been pirated without extensive investigation, that is, reverse engineering and very detailed analysis by experts. Accordingly, it is desirable to manufacture a semiconductor chip with features therein for easy identification.
From the above it is seen that a method of fabricating semiconductor devices that is easy, reliable, cost effective, and identifiable is often desired.